Integrated circuits are chemically and physically integrated into a substrate, such as a silicon or gallium arsenide wafer, by patterning regions in the substrate, and by patterning layers on the substrate. These regions and layers can be conductive, for conductive path and bond pad fabrication. They can also be of different conductivity types, which is essential for transistor and diode fabrication. Up to a thousand or more devices are formed simultaneously on the surface of a single wafer of semiconductor material.
For high density devices of submicron feature sizes it is essential to start with a flat semiconductor wafer and to maintain a planarized surface at various fabrication steps. If the process steps of device fabrication are performed on a wafer surface that is not uniform and planarized, various problems can occur which may result in a large number of inoperable devices.
Methods used to ensure the wafer surface planarity included forming an oxide such as borophosphosilicate glass (BPSG) layer on the wafer surface, then heating the wafer to reflow and planarize the oxide layer. This "reflow" method of planarizing the wafer surface was sufficient with fairly large device geometries, but as the technology allowed for smaller device feature sizes, this method produced unsatisfactory results.
Another method which has been used to produce a planar wafer surface is to use the oxide reflow method described above, then spin coat the wafer with photoresist. The spin coating of the material on the wafer surface fills the low points and produces a planar surface from which to start. Next, a dry etch, which removes photoresist and oxide at a rate sufficiently close to 1:1, removes the photoresist and the high points of the wafer, thereby producing a planar oxide layer on the wafer surface.
Most recently, chemical mechanical planarization (CMP) processes have been used to planarize the surface of wafers in preparation for device fabrication. The CMP process involves holding a thin flat wafer of semiconductor material against a rotating wetted polishing pad surface under a controlled downward pressure. A polishing slurry such as a mixture of either a basic or acidic solution used as a chemical etch component in combination with alumina or silica particles may be used. A rotating polishing head or wafer carrier is typically used to hold the wafer under controlled pressure against a rotating polishing platen. The polishing platen is typically covered with a polishing pad material such as blown polyurethane.
Such apparatus for polishing thin flat semiconductor wafers are well known in the art. U.S. Pat. Nos. 4,193,226 and 4,811,522 to Gill, Jr. and U.S. Pat. No. 3,841,031 to Walsh, for instance, disclose such apparatus.
Deposited conductors are an integral part of every integrated circuit, and interconnect lines formed from conductive materials provide the role of surface wiring to conduct current. Specifically, the deposited conductors are used to electrically couple various components that are formed in the surface of the wafer, and also for use as bond pads for the semiconductor device. A recent development in producing these metal features is to use a damascene procedure, as described in U.S. Pat. No. 5,065,273 by Rajeevakumar. A damascene process produces conductive interconnects and other features which are directly defined by chemical mechanical planarization without a reactive ion etch (RIE) process, and has the potential to fabricate submicron geometry interconnects. A conventional damascene process, as shown in FIGS. 1-3, begins by forming a dielectric 10, such as oxide, over a wafer substrate 12. The dielectric 10 is patterned, for example using lithography to form a photoresist layer 14. Referring to FIG. 2, "troughs" 20 are formed in the dielectric 10 defined on two sides by the dielectric, and on the bottom by the substrate 12 or a barrier layer (not shown) as described below. A conformal blanket layer of conductive material 22 such as doped polycrystalline silicon or a metal such as copper or tungsten is deposited over the wafer surface. Finally, the wafer surface is polished thereby removing the conductive material overburden while leaving the conductive material 30 in the planar dielectric surface 10 as shown in FIG. 3.
FIG. 4 shows another feature which can be formed with a similar damascene process. A contact hole 40 in a dielectric 10 (such as oxide) to an active area 42 of the substrate 12 is plugged with a conductive material 44 such as tungsten. A conductive line (not shown) is then contacted to the metal plug 44.
One problem that occurs during the fabrication of a semiconductor device using damascene of a conductive material such as copper or tungsten is "dishing" of the comparatively large bond pads, contacts, and other large metal surfaces. FIG. 5 shows a top view optical micrograph of the dishing 50 in a tungsten film which can occur on a bond pad 52 using a normal damascene process. The dishing 50 occurs as the polishing pad removes more of the material at the center of the large feature than at the outer edges. Due to the elasticity of the polishing pad, polishing will continue at the bond pads 52 and other large metal feature areas when the metal and dielectric substrate interface is reached during a CMP process. The material in the middle of the feature, therefore, is thinner than at the edges. In extreme cases, the material in the middle of the feature can be completely abraded away by the polishing pad. The bond pad 52 overlies a nonconductive substrate 54, so soldering the bond wire to a bond pad having this dishing effect produces a physically and electrically weak coupling. The electrical resistance can be increased as the surface area of the contact between the bond wire and the bond pad is greatly decreased.
A need remains for improved methods of forming conductive features on semiconductor wafers using a damascene procedure which reduces or eliminates dishing of the feature surface.